1. Field of the Invention
The present invention relates to a thin film transistor for use in a liquid crystal display device, and more particularly, to a method of fabricating a top gate type thin film transistor (TFT) having low temperature polysilicon.
2. Discussion of the Related Art
In general, silicon is classified into amorphous silicon and crystalline silicon depending on the silicon's crystalline state. It is possible for the amorphous silicon to be formed as a thin film on a glass substrate. Because the glass substrate has a low melting point, the amorphous silicon is deposited at a low temperature on the glass substrate. The amorphous silicon is generally used for a switching device, such as a thin film transistor in pixel of a liquid crystal display panel. However, a thin film of amorphous silicon has some disadvantages, such as decreased reliability, decreased electrical characteristics when used in a switching device, and is difficult to redundantly form in each pixel of a very large area liquid crystal display panel.
A liquid crystal display panel can be utilized for a laptop computer, a wall-mounted TV or other commercial applications. However, since these commercial products need a large-sized display, high resolution, and high color image rendering capability, the thin film transistor used as a switching device in each pixel has to have superior electrical characteristics, such as high field effect mobility, reliability against high frequency, and low leakage current. The demand for such superior electrical characteristics has forced thin film transistor producers to research and develop polycrystalline silicon (i.e., polysilicon) for use in the thin film transistor.
Recently, a low temperature polysilicon thin film transistor (LTPS-TFT) has been widely attracting attention for system-on-panel-integration in CMOS process. Such an LTPS-TFT can be used in an active matrix type liquid crystal display device. However, at this time, it is necessary to enhance the quality of a gate insulation layer for the purpose of improving the operating characteristics of the low temperature polysilicon thin film transistor (LTPS-TFT).
FIG. 1 is a cross-sectional view illustrating a low temperature polysilicon thin film transistor (LTPS-TFT) according to the related art. As shown in FIG. 1, the LTPS-TFT has a polysilicon active layer 16 over a substrate 10 and a gate electrode 20 over the polysilicon active layer 16 to make a top gate type thin film transistor. Because the polysilicon active layer 16 is formed by applying heat to amorphous silicon, the gate electrode 20 is formed in a later step after the step of forming the polysilicon layer 16 to protect the gate electrode 20 from the applied heat. More specifically, since the metal of the gate electrode 20 may be affected by the applied heat, the polysilicon layer 16 is formed and then the gate electrode 20 is formed over the polysilicon active layer 16 thereafter. Between the active layer 16 and the gate electrode 20, a silicon oxide 18 (often referred to as a gate insulation layer) is formed. The polysilicon active layer 16 is divided into an active portion 16a in the middle and highly-doped source/drain portions 16b on left and right sides. The gate electrode 20 is formed to correspond in position to the active portion 16a. Source and drain electrodes 28 and 30 are formed over the substrate 10 to contact the highly-doped source/drain portions 16b, respectively.
The polysilicon may be used for a bottom gate type thin film transistor. The bottom gate type thin film transistor usually has a gate electrode on a substrate, a gate insulation layer on the gate electrode, and an amorphous silicon layer on the gate insulation layer especially over the gate electrode. The amorphous silicon layer is then crystallized through the laser crystallization to be the polysilicon layer. At this time, however, there are some disadvantages, i.e., the step of the gate electrode causes the nonuniformity of the polysilicon. Therefore, the bottom gate type thin film transistor having such polysilicon represents bad electrical characteristics so that the polysilicon layer is hardly used for the bottom gate type thin film transistor.
FIGS. 2A to 2E are cross-sectional views illustrating process steps of forming a low temperature polysilicon thin film transistor (LTPS-TFT) having a top gate according to the related art. As shown in FIG. 2A, a buffer layer 12 is first deposited on the substrate 10. The buffer layer 12 is formed of one of silicon nitride and silicon oxide. The buffer layer 12 prevents alkali substances and the like in the substrate 10 from spreading into a silicon layer that is subsequently formed. Thereafter, an amorphous silicon (a-Si:H) layer 14 is sequentially deposited on the buffer layer 12, and then crystallized. There are a lot of methods of crystallizing amorphous silicon including, for example, laser crystallization. Besides laser crystallization, other low temperature crystallization methods can be applied to the amorphous silicon 14 for silicon crystallization.
Referring to FIG. 2B, the crystallized silicon layer (i.e., a polysilicon layer) is patterned to from an island-shaped active layer 16. The polysilicon active layer 16 is divided into a first portion 16a and second portions 16b. The first portion 16a is located in the middle of the polysilicon active layer 16, and the second portions 16b are located on both right and left sides of the first portion 16a. The first portion 16a is often referred to as an active portion, and the second portions 16b are often referred to as ohmic contact portions. A gate insulation layer 18 is formed on the buffer layer 12 to cover the polysilicon active layer 16. The gate insulation layer 18 is made of silicon oxide (SiO2) using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
Referring to FIG. 2C, a gate electrode 20 is formed on the gate insulation layer 18 to define the active portion 16a. Thereafter, the gate insulation layer 18 is patterned into a gate-electrode shape, but this patterning process can be omitted so that the gate insulation layer 18 can remain on the buffer layer 12 while covering the polysilicon active layer 16. After forming the gate electrode 20 right above the active portion 16a, dopant ions, such as p-type ions, are doped into the second portions 16b. Since the gate electrode 20 is disposed above the first portion 16a and acts as an ion stopper, the dopant ions, such as p-type ions, are not doped into the first portion 16a. The doped areas, the second portions 16b, become highly-doped source/drain contact areas where source and drain electrodes are contacted in a later step.
Referring to FIG. 2D, an interlayer insulator 22 is formed over the entire substrate 10 to cover the gate electrode 20, the gate insulation layer 18 and the active layer 16. A first contact hole 24 and a second contact hole 26 are formed through the interlayer insulator 22, thereby exposing the second portions 16b (i.e., the highly-doped source/drain portions) of the polysilicon active layer 16, respectively. The exposed second portions 16b are source and drain regions on which source and drain electrodes are formed, respectively.
Referring to FIG. 2E, a source electrode 28 and a drain electrode 30 are formed on the interlayer insulator 22. The source and drain electrodes 28 and 30 electrically contact the exposed second portions 16b of the polysilicon active layer 16, respectively, through the respective first and second contact holes 24 and 26. This completes a top gate type thin film transistor having a low temperature polysilicon layer.
However, the method of forming the low temperature polysilicon thin film transistor includes some disadvantages. The gate insulation layer of silicon oxide is formed on the polysilicon active layer, and then the gate electrode is formed on the silicon oxide gate insulation layer. At this time, interface states are inevitably formed between the gate insulation layer and the polysilicon active layer. Furthermore, the operating characteristics of the LTPS-TFT may degrade due to the fact that the silicon oxide gate insulation layer has low resistance against F-N stress (Fowler-Nordheim stress).
FIG. 3 is a graph showing current characteristics of silicon oxide layer in accordance with gate voltage and gate current density applied to a metal of the Metal-Oxide-Semiconductor (MOS) structure. As shown in FIG. 3, as the gate voltage is applied to the metal of the MOS structure, the gate current density applied to the silicon oxide layer is divided into three different dominant regions; a leakage current dominant region (gate insulation layer quality dependent region), a F-N tunneling dominant region that is a peculiar current mechanism of silicon oxide, and a hard breakdown region where the silicon oxide layer loses its dielectric characteristic. The current passing through the silicon oxide layer is represented by summing up the leakage current value and the tunneling current value.
To test the reliability of the silicon oxide layer, the voltage and current level in the F-N tunneling dominant region is continuously applied to the silicon oxide layer such that an F-N stress is continuously applied to the silicon oxide layer. Thereafter, the point of time of breakdown is measured in the silicon oxide layer. For example, the constant current in the F-N tunneling dominant region is applied to the silicon oxide layer for a long time. The time of breakdown of the silicon oxide layer can be represented by current density×time to dielectric breakdown=charge to breakdown. As the value of charge to breakdown increases, so does the reliability of the silicon oxide layer. The LTPS-TFT fabricated through the related art of FIGS. 2A–2E has a silicon oxide layer 18 shows a very low resistance to F-N stress.